In recent years, in imaging apparatuses such as digital still cameras, there is a plurality of modes including a low frame rate mode for capturing a still image, and a high frame rate mode for capturing a moving image and for liquid crystal monitor display.
Among these modes, especially in the high frame rate mode, the frame rate may sometimes be adjusted to match with a signal processing period of subsequent stages and the like, and thus a read/output system provided with an invalid signal period in which no video signal is output may sometimes be employed.
That is, when video signals of frames F1, F2, . . . are read at a predetermined frame rate, a waiting time may be caused after the frame F1 to be read has been read to timing when the frame F2 to be next read is read. Such a waiting time is the invalid signal period, and a period in which a video signal of each frame is read is a valid signal period. In the past, clock signals necessary for transfer of these video signals are output during both of the valid signal period and the invalid signal period.
However, in recent years, there have been strong demands for reduction of power consumption, and various proposals have been made. For example, a technology has been proposed, which stops the clock signals for reading the video signals during the invalid signal period because the invalid signal period having no video signal output does not require signal outputs from a solid-state imaging device, so that the power consumption is reduced (see Patent Document 1).
However, in the technology described in Patent Document 1, when the stopped clock signal for reading a video signal is re-started, a period in which a power supply current to a driver that is operated based on the clock signal becomes unstable occurs, and thus a clamp level that clamps a back level varies and the black level may become unstable.
Regarding this point, a technology to make the black level stable has been proposed (see Patent Document 2).